VLSI PROJECTS(2016)S.NO TECHNOLOGY TITLE NAME YEAR
1 FRONT END Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding 2016 2 FRONT END Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation 2016 3 FRONT END Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic 2016 4 FRONT END A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications 2016 5 FRONT END A Method to Design Single Error Correction Codes With Fast Decoding for a Subset of Critical Bits 6 FRONT END On Efficient Retiming of Fixed-Point Circuits 2016 7 FRONT END Concept, Design, and Implementation of Reconfigurable CORDIC 2016 8 FRONT END Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks 2016 9 FRONT END Low-Power Parallel Chien Search Architecture Using a Two-Step Approach 2016 10 FRONT END An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24,12) Extended Golay Code 2016 11 FRONT END Memory-Reduced Turbo Decoding Architecture Using NII Metric Compression 2016 12 FRONT END Multiple Constant Multiplication Algorithm for High-Speed and Low-Power Design 2016 13 FRONT END Design and Analysis of Inexact2016 Floating-Point Adders 2016 14 FRONT END A Mixed-Decimation MDF Architecture for Radix-2k Parallel FFT 2016 15 FRONT END A Modified Partial Product Generator for Redundant Binary Multipliers 2016 16 FRONT END A Cellular Network Architecture With Polynomial Weight Functions 2016 17 FRONT END .A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO 2016 18 FRONT END High Speed Hybrid Double Multiplication Architectures Using New Serial-Out Bit- Level Mastrovito Multipliers 2016 19 FRONT END Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication 2016 20 FRONT END A High-Speed FPGA Implementation of an RSD-Based ECC Processor 2016 21 FRONT END VLSI Design for Convolutive Blind Source Separation 2016 22 FRONT END High-Speedand Energy-Efficient Carry Skip Adder Operating Under a Wide Rangeof Supply Voltage Levels 2016 23 FRONT END Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding 24 FRONT END Hardware and Energy-Efficient Stochastic LU Decomposition Scheme for MIMO Receivers 25 FRONT END Hybrid LUT/Multiplexer FPGA Logic Architectures 2016 26 FRONT END Performance/Power Space Exploration for Binary64 Division Units 2016 27 FRONT END A High Throughput List Decoder Architecture for Polar Codes 2016 28 FRONT END A Novel Coding Scheme for Secure Communications in Distributed RFID Systems 2016 29 FRONT END Arithmetic algorithms for extended precision using floating point expansions 2016 30 FRONT END Digital Multiplierless Realization of Two-Coupled Biological Hindmarsh–Rose Neuron Model 31 BACK END A Low Power Trainable Neuromorphic Integrated Circuit That Is Tolerant to Device Mismatch 32 BACK END A 55-GHz-Bandwidth Track-and-Hold Amplifier in 28-nm Low-Power CMOS 2016 33 BACK END A Low-Power Incremental Delta–Sigma ADC for CMOS Image Sensors 2016 34 BACK END Low-Power ASK Detector for Low Modulation Indexes and Rail-to-Rail Input Range 2016 35 BACK END . A Low-Power Robust Easily Cascaded PentaMTJ-Based Combinational and Sequential Circuits 36 BACK END PNS-FCR: Flexible Charge Recycling Dynamic Circuit Technique for Low-Power Microprocessors 37 BACK END Low-Power Variation-Tolerant Nonvolatile Lookup Table Design 2016 38 BACK END Dual Use of Power Lines for Design-for-Testability—A CMOS Receiver Design 2016 39 BACK END One-Cycle Correction of Timing Errors in Pipelines With Standard Clocked Elements 2016 40 BACK END High performance VLSI architecture for 2-D DWT using lifting scheme 2016 TITLES FOR 2015 1. LOW-COST HIGH-PERFORMANCE VLSI ARCHITECTURE FOR MONTGOMERY MODULAR MULTIPLICATION 2. A LOW-POWER HYBRID RO PUF WITH IMPROVED THERMAL STABILITY FOR LIGHT WEIGHT APPLICATIONS 3. LOW-POWER AND AREA-EFFICIENT SHIFT REGISTER USING PULSED LATCHES 4. LOW-POWER PROGRAMMABLE PRPG WITH TEST COMPRESSION CAPABILITIES 5. A NOVEL AREA-EFFICIENT VLSI ARCHITECTURE FOR RECURSION COMPUTATION IN LTE TURBO DECODERS 6. RELIABLE AND ERROR DETECTION ARCHITECTURES OF POMARANCH FOR FALSE-ALARM-SENSITIVE CRYPTOGRAPHIC APPLICATIONS 7. RECURSIVE APPROACH TO THE DESIGN OF A PARALLEL SELF-TIMED ADDER 8. FAULT TOLERANT PARALLEL FFTS USING ERROR CORRECTION CODES AND PARSEVAL CHECKS 9.IMPLEMENTATION OF 256 BIT RNG IN FPGA USING EFFICIENTRESOURCE UTILIZATION 10. LOW-POWER, HIGH-THROUGHPUT, AND LOW-AREA ADAPTIVE FIR FILTER BASED ON DISTRIBUTED ARITHMETIC 11. AGING-AWARE RELIABLE MULTIPLIER DESIGN WITH ADAPTIVE HOLD LOGIC 12. REVERSE CONVERTER DESIGN VIA PARALLEL-PREFIX ADDERS: NOVEL COMPONENTS, METHODOLOGY, AND IMPLEMENTATIONS 13. COMMENTS ON “SELF-CHECKING CARRY-SELECT ADDER DESIGN BASED ON TWO-RAIL ENCODING” 14.AREA-EFFICIENT FIXED-WIDTH SQUARER WITH DYNAMIC ERROR-COMPENSATION CIRCUIT 15. A 5.8-GHZ WIDEBAND TSPC DIVIDE-BY-16/17 DUAL MODULUS PRESCALER 16. NON-BINARY ORTHOGONAL LATIN SQUARE CODES FOR A MULTILEVEL PHASE CHARGE MEMORY (PCM) 17. A GENERALIZED ALGORITHM AND RECONFIGURABLE ARCHITECTURE FOR EFFICIENT AND SCALABLE ORTHOGONAL APPROXIMATION OF DCT 18. ENERGY AND AREA EFFICIENT THREE-INPUT XOR/XNORS WITH SYSTEMATIC CELL DESIGN METHODOLOGY 19. IMPLEMENTATION AND COMPARISON OF EFFECTIVE AREA EFFICIENT ARCHITECTURES FOR CSLA(256 BIT) 20. Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic IEEE VLSI PROJECTS 2014-15 MSR01 An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis 2014 MSR02 Area-Delay Efficient Binary Adders in QCA 2014 MSR03 Area-Delay-Power Efficient Fixedfacebook.com/m.s.r.project-Point LMS Adaptive Filter With Low Adaptation-Delay 2014 MSR04 Power- and Area-Efficient Approximate Wallace Tree Multiplier for Error-Resilient Systems 2014 MSR05 Area–Delay–Power Efficient Carry-Select Adder 2014 MSR06 Transaction-based SoC Design Techniques for AMBA AXI4 Bus Interconnects using VHDL 2014 MSR07 Low-Power Programmable PRPG With Test Compression Capabilities 2014 MSR08 High Speed Vedic Multiplier Designsa Review 2014 MSR09 4-2 Compressor Design with New XOR-XNOR Module 2014 MSR010 Design and Estimation of delay, power and area for Parallel prefix adders 2014 MSR011 Fast Radix-10 Multiplication Using Redundant BCD Codes 2014 MSR012 FPGA Based Partial Reconfigurable Fir Filter Design2014 MSR013 Fast Sign Detection Algorithm for the RNS Modulo Set {2n+1 − 1, 2n − 1, 2n} 2014 MSR014 Design of a Low-Error Fixed-Width Radix-8 Booth Multiplier 2014 MSR015 A Novel Parallel Multiplier for 2’s Complement Numbers Using Booth’s Recoding Algorithm 2014 MSR016 A Decimal / Binary Multi-operand Adder using a Fast Binary to Decimal Converter 2014 MSR017 High Speed Multiplier for FIR Filter Design using Window 2014 MSR018 Design of Efficient Binary Comparators in Quantum-Dot Cellular Automata 2014 MSR019 Using FPGAs to Implement Asynchronous Pipelines 2014 MSR020 Improved 8-Point Approximate DCT for Image and Video Compression Requiring Only 14 Additions MSR021 High-Throughput Multi standard Transform Core Supporting PEG/H.264/VC-1 Using Common Sharing Distributed Arithmetic 2014 MSR022 ASIC Implementation of DDR SDRAM Memory Controller 2013 MSR023 Multi operand Redundant Adders on FPGAs.2013 MSR024 Design and Simulation of ZIGBEE Transmitter Using Verilog 2013 MSR025 CORDIC Designs for Fixed Angle of Rotation. 2013 MSR026 Design A DSP Operations Using Vedic Mathematics. 2013 MSR027 Design And Implementation Of 32 Bit Unsigned Multiplier Using CLA And CSLA. 2013 MSR028 Design And Implementation Of Truncated Multipliers For Precision Improvement. 2013 MSR029 VLSI Implementation Of Fast Addition Using Quaternary Signed Digit Number System 2013 MSR030 Design of High Speed Low Power Multiplier Using Reversible Logic: A Vedic Mathematical Approach. MSR031 Design Of high Performance 64 Bit MAC Unit. 2013 MSR032 High Performance Hardware Implementation Of AES Using Minimal Resources.2013 MSR033 Implementation And Comparison Of Effective Area Efficient Architectures For CSLA. 2013 MSR034 Novel High Speed Vedic Mathematics Multiplier Using Compressors. 2013 MSR035 FPGA Implementation of 16-Point Radix-4 Complex FFT Core Using NEDA 2013
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